This is a big day for the server wars. AMD finally released its new 16-core processors: code-named ""Interlagos"" and ""Valencia."" On the same day, Intel rolled out its new Sandy Bridge-E processors and there is already lots of speculation over whether or not their extra power is worth the price. But today the spotlight is on AMD. Its 16-core Opteron„¢ line is a much-anticipated release. Sinceas early as 2009, we have been hearing about AMD™s plans for 16-core processors. Interlagos is officially known as the Opteron„¢ 6200, a 12- or 16-core x86 processor that is compatible with Socket G34 motherboards (Magny-Cours & Opteron„¢ 6100.) Not only does the absolute number of cores enable far superior performance compared to the current Opteron„¢ 6100 series, butInterlagosis one of the products taking advantage of AMD™s newBulldozerCPU. AMD says that its new processors have been designed to provide enterprises with enhanced options, including:

• Better performance for business(up to 84%)
• Increased scalability for virtualization (up to 73% more memory bandwidth)
• Greater economic efficiency for cloud(half power consumption per core, 2/3 less real estate space, and 2/3 lower platform price)

Currently, Bulldozer processors are being utilized by two systems in AMD™s server segment:

• Dual Chip 16-core Opteron„¢ Interlagos (for Socket G34)
• Single Chip 4-8 core Valencia(for Socket C32)

The Bulldozer core design is compatible with the 6100 series platforms and infrastructure. However, it departs from the traditional dual-core processor in the way the cores interact with one another. A standard dual-core processor duplicates a CPU™s execution, as well as the top-level cache. The two cores are linked via a lower-level cache. On the Bulldozer, integer units remain separate, but the setup is different from the older Istanbul core design. Bulldozer is designed to share resources, including its scheduler, decode hardware, and floating point unit. The new Interlagos CPUs feature a multi-chip design where the processor is built by joining together two six- or eight-core Valenciadies. The Interlagos Opteron„¢ 6200 system is comprised of eight Bulldozer modules, each containing two independent integer processors. However, for each module/pair of processors there is only a single floating point unit (FPU) and a shared set of fetch and decode units. AMD believes that this newdesign will result in a much higher integer performance because the chip is better able to make use of available throughput. Regarding the shared FPU for two cores, AMD claims that since FPU code only comprises about 40% of a server workload, an efficiently-shared FPU is capable of managing these workloads with little more than a minor blow to performance. It is also important to note that the Bulldozer FPU is noticeably larger than its counterpart aboard the Istanbul. A nice way of conceptualizing the Bulldozer™s design is that œ(i)t has more than one core, but not quite two. With all of this said “ given the early benchmarks, unfamiliar architecture, and bugs common to first designs “ it is likely that the reality of the Bulldozer and its server systems will not immediately match up to its theoretical performance. However, it will be interesting to see what happens going forward. AMD has some room to maneuver here as its products still fill a somewhat distinctive need from Intel's core lines. But Intel is certainly no sloucher. The Sandy Bridge-E processors with only six-cores (i7-3960X Extreme Edition) hit 3.3GHz with the potential to jump to 3.9GHz with TurboBoost, and it also features 15MB of cache. Intel is looking to maximize the gap in CPU performance between its products and the competition (i.e. AMD.) And while we can't reveal any of the preliminary information yet, they have big plans for their new products next year. AMD doesn't have long to feel out a new direction with their 16-core processors, and they will need to run with their ball quickly if they want to maintain the momentum these processors can provide. Quick Facts

Official Name	Opteron„¢ 6200
# of Cores	12 or 16
Instruction Set Architecture	x86
Core Design	Multi-Chip joining two 6- or 8-core Valenciadies
DRAM	Quad-Channel DDR3
Other Features	Turbo Core Dynamic Overclocking Technology
	Configurable TDP
	Advanced Power Saving Options