Intel MIC and its Comprehensive Networking Strategy

Last week we talked about the upcoming release of Intel’s Xeon E5 processor family. This week, we have some even more important announcements regarding Intel MIC and the strategic direction that Intel is headed regarding high performance computing.

Image of the Aubrey Isle Die used in the Intel MIC "Knights Ferry"

Die shot of ‘Aubrey Isle,’ the silicon chip included in the Intel MIC ‘Knights Ferry’ development platform

Intel “MIC” (for Many Integrated Core) co-processor architecture is a leading initiative in Intel’s move into the realm of HPC and parallel computing. At Supercomputing 2011, Intel had an opportunity to show off the advantages of Intel MIC for a variety of computing tasks, including weather modeling, tomography, protein folding and advanced materials simulation. Intel beamed with joy unveiling their 50 core “Knights Ferry” prototype last year.

This year we are expected to see the next product in this line: the much-anticipated commercial “Knights Corner.” Early presentations of “Knights Corner” showed that the Intel architecture is capable of delivering over 1 TFLOPs of double precision floating point performance, the highest performance level achieved for a single processing chip. With this, Intel will finally have an answer to NVIDIA’s Tesla line and AMD’s Fusion APUs.

Intel MIC is also part of a larger strategy which has become clearer in recent weeks. With the acquisition of the Infiniband technology line from QLogic back in January of 2012 and the announcement of the Crystal Forest platform earlier this week, it is obvious that Intel hopes 2012 will be the year it starts to establish a solid position in the high performance computing space.

Despite the fact that we are on the cusp of the Romley / Xeon E5 release, this almost overshadows that launch in a way because it is indicative of a serious expansion for Intel into the HPC, networking, heterogeneous computing, and data center industries. Intel has even claimed that MIC outperforms GPUs when it comes to parallel computing, which means that NVIDIA in particular, as the leading provider of GPU computing solutions, may have some serious competition to contend with in the near future. And, with dedicated chipsets geared towards increasing data center network speeds without adversely affecting performance or security, it’s not hard to see how Intel’s strategy is intended to play out.

When you couple all of this with the fact that, traditionally, Intel has risen to be the dominant force in virtually every market it has entered, the future of enterprise IT has some very interesting possibilities.

Other comments made by Raj Hazra (either in the video or in the original Intel press release):

  • “Knights Corner,” will be manufactured using Intel’s latest 3-D Tri-Gate 22nm transistor process. Featuring over 50 cores, Intel MIC will offer both high performance from an architecture specifically designed to process highly parallel workloads and compatibility with existing x86 programming model and tools.
  • The “Knights Corner” co-processor is very unique as, unlike traditional accelerators, it is fully accessible and programmable. In this way it resembles a fully functional HPC compute node, visible to applications as though it was a computer that runs its own operating system independent of the host OS.
  • A major benefit of the Intel MIC architecture is the ability to run existing applications without the need to port the code to a new programming environment. This will allow scientists to use both CPU and co-processor performance simultaneously with existing x86 based applications, dramatically saving time, cost and resources that would otherwise be needed to rewrite them to alternative proprietary languages.

HPC @ Intel 2011 – video with more info on Intel and MIC (released Summer 2011 outlining Intel’s future development in the high performance computing industry)