PCIe: An Overview

PCI/PCIX Fundamentals

Peripheral Component Interconnect, (PCI), is a computer bus or expansion card standard, for connecting hardware devices. The three versions - PCI, PCI-X and PCIe - perform at varying speeds and specifications. The parallel topology of PCI and PCI-X requires a wider physical layer (actual wires, strands and pins) but allows for signals to travel (X) channel times faster, compared to serial communication protocols (PCIe). PCIe uses a serial interface and allows for point-to-point interconnections between devices using directly wired interfaces between these connection points.

The oldest standard, PCI, uses a shared bus topology, wherein all components must use the same bus network for all their processes. PCI boasts a 64bit, 66MHz combination with a peak theoretical bandwidth of 512MB/s. The lower bandwidth capability of PCI, compared to PCI-X and PCIe, makes it virtually obsolete.

PCI-X is a double-wide version of PCI, running double the clock speed of PCI from 66MHz to 133MHz. The theoretical maximum communication speed using PCI-X is 1.06 GB/s, compared to 133 MHz for PCI; the gap between the theoretical and actual maximum is significant. Backward compatible with PCI, it improves the fault tolerance of PCI, allowing faulty cards to be reinitialized. Developed for the higher bandwidth demanded by modern servers, it retains the topology and electrical implementation of PCI.

Early selection criteria

Before the development of high speed serial communication, three factors dominated the choice of serial v parallel protocols:

• Speed: Parallel communication dominated serial, in terms of speed, given the physical medium. A wider path, allowing a higher bit rate, translating into higher data rates. Clock skew, the interval of clock signal arrival at different components, limits this factor by reducing the transmission speed to the speed of the slowest link.
• Cable length: Crosstalk creates interference between parallel lines and grows as cable length grows, limiting the theoretical length of any given cable.
• Complexity: Creating a parallel link in any board is relatively simple compared to a similar serial link.

Because PCI and PCI-X use a shared bus topology, all devices are attached to the same bus and host. This configuration requires bus arbitration in order to determine what device has access to the bus and CPU. The cost and implementation advantages of a shared bus begin to disappear as the bandwidth and workload requirements of devices increase.

The wider physical layer of parallel communication translates directly into higher cost for cable length. Wider cables require more physical pins on the motherboard. As consumer demand increases, the increased cost of cable plays heavily in any cost benefit analysis. Using a parallel communication topology, PCI and PCI-X have a larger footprint on the motherboard, making them less attractive going forward.

PCIe Intro

Often confused with PCI-X, PCIe (PCI Express) uses a serial link topology and is the latest standard for expansion cards available on personal computers. With software, PCIe is backward compatible with PCI/PCI-X although electrical signaling and bus protocol differences require a different mechanical form factor and new motherboards. PCIe 1.0 (x1 lanes), offers 250 MB/s in each direction. With a maximum allowable 32 lanes (x32), 8 GB/s is supported in each direction. PCIe also requires less complex trace routing architecture than does PCI-X.

One of PCIe's nicest features is the ability to aggregate multiple individual lanes to form a single link. A link composed of a single lane is called a x1 (read: by one) link; a link composed of two lanes is called a x2 link; four lanes is called a x4 link, etc. PCIe supports x1, x2, x4, x8, x12, x16, and x32 link widths. In other words, two lanes (x2) could be coupled together to form a single link capable of transmitting two bytes at a time, thus doubling the link bandwidth. Likewise, you could combine four lanes (x4), or eight lanes (x8), and so on.

You can install PCI Express slots in larger slots but not smaller ones. For example, you can install a PCI Express x1 adapter into an x16 slot (but will still operate at the x1 speed), but you cannot insert an x16 adapter into an x1 slot. This compatibility is shown in the table below.

High performance computing requires high bandwidth and 3D rendering involves moving a lot of data around very quickly between the video card, the CPU, and main memory. Using older architectures requires higher RAM requiring the GPU to go out to main memory to get rendering data. PCIe allows this data to flow through without the high RAM requirement.

In Q4 of 2006, PCI-SIG (Special Interest Group) released the 2.0 update to the PCI Express Base Specification. The most significnt change is an increase in the signaling rate to 5.0GT/s (double that of the PCI Express 1.x specification of 2.5GT/s). This effectively doubles the maximum theoretical bandwidth of PCI Express and creates the additional data throughput capabilities that tomorrow's demanding systems will need for peak performance.

The PCI Express interface supports interconnect widths of x1, x2, x4, x8, x16, and x32 (PCI-E x32 slots are rarely seen because of their exceptional length. PCI Express 2.0 permits the same bandwidth in PCI-E x16 form factor).